1. Field of the Invention
The present invention relates to a semiconductor device such as a CMOS-type static random access memory (SRAM) device.
2. Description of the Related Art
Generally, one SRAM cell uses a flip-flop constructed by two cross-coupled inverters and two transfer transistors. In this case, each of the inverters has a load element and a drive transistor.
In view of the power consumption, a CMOS-type SRAM cell has been developed where the above-mentioned load element is constructed by a P-channel MOS transistor, while the above-mentioned drive transistor is constructed by an N-channel MOS transistor. This will be explained later in detail.
In the prior art CMOS-type SRAM cell, however, since the voltage at a well is not surely fixed to a definite voltage within the cell, a latch-up phenomenon may occur. In order to suppress or avoid such a latch-up phenomenon, the P-type impurity regions of an N-type well have to be sufficiently separated from the N-type impurity regions of a P-type well, which would reduce the integration density.
It is an object of the present invention to provide. a semiconductor device such as a CMOS-type SRAM device capable of suppressing or avoiding a latch-up phenomenon.
According to the present invention, in a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and is connected to the well, so as to fix a voltage at the well.